As integrated circuits are produced with greater and greater levels of circuit density, improved testing methodologies have become necessary. One such methodology, which implements boundary scan testing of external or internal chip networks, has become to be in general use in the industry. The most common method is elaborated in the IEEE standard 1149.1, defines a TAP (Test Access Port) to implement a set of test functions, providing test access at chip level as well as at the printed circuit board (PBC) level. While boundary scan testing is prevalent, limitations still exist. In particular, evaluation of digitally encoded values (binary/signed or two's complement) where such values are not known a-priori, presents challenges in an Automatic Test Equipment (ATE) test environment where digitally based tests are completely deterministic. It is therefore desirable to have an improved system and method for integrated circuit testing to address the aforementioned shortcomings.